1. Field of the Invention
The present invention relates to a semiconductor device having a fuse program circuit that includes a fuse element storing fixed information, and particularly to a construction for implementing a fuse program circuit operating with low power consumption and small occupation area.
2. Description of the Background Art
Fuse program circuit is employed in semiconductor integrated circuit devices for various purposes. The fuse program circuit generates an output signal of which state is fixedly set by blowing or non-blowing a fuse element. For example, such fuse elements are employed for trimming a constant of an analog circuit. Programming (i.e., blowing or non-blowing) of the fuse elements is performed, for example, for adjusting a current driving power of a transistor element, a supplying current quantity of a reference current source, a level of a reference voltage produced by a reference voltage supply and others. The fuse program circuit is also used for trimming a resistance value of a resistance element.
In a digital circuit, a similar adjustment is performed. A semiconductor memory employs a fuse program circuit for storing a fault address used for replacing a faulty cell with a redundant cell. By using the fuse program circuit, the circuit operation characteristics are optimized, and the faulty cell is repaired so that product yield may be improved.
Conventionally, fuse program circuits have generally used LT (Laser Trimming) fuses that can be blown by irradiation with a laser beam. A laser apparatus is used to blow the LT fuses according to program information for executing fuse programming.
Japanese Patent Laying-Open No. 2003-016797 (Reference 1) has disclosed a construction using a fuse program circuit as a fault address storage circuit for redundant cell repair. In Reference 1, there are provided a fuse block for performing fuse programming of a fault address, a scan shift circuit externally inputting fault addresses in series and internally outputting them in parallel, and a selector circuit for selecting one of outputs of the fuse block and the scan shift circuit according to a mode instructing signal.
Before the programming of the fuse elements, it is internally determined whether redundant repair will be reliably performed, for intending to improve the yield.
Japanese Patent Laying-Open No. 11-340434 (Reference 2) has disclosed a construction in which elements or interconnects are arranged hierarchically with and lower than fuse elements. By arranging the elements below the fuse elements, it is intended to reduce a device chip area. In Reference 2, an impact interrupt layer made of a material having a higher melting point than the fuse elements is arranged below the fuse element, so that thermal and physical impacts that may be applied to elements at the lower layer at the time of blowing of the fuse elements may be prevented. A stacked structure formed of a heat sink layer and a thermal resistance layer is used for the impact interrupt layer.
Japanese Patent Laying-Open No. 05-267464 (Reference 3) has disclosed a structure of a fuse circuit that blows a fuse element by a current. In Reference 3, a select circuit connects one of a fuse trimming circuit including fuse elements and an internal circuit to a common power supply pad according to a control signal. It is intended to reduce the number of pads, for reducing a chip occupation area and a probability of occurrence of connection failure between the pad and a pin.
Japanese Patent Laying-Open No. 2002-042482 (Reference 4) has disclosed a construction, in which fuse elements and internal circuits share a power supply. In Reference 4, an output signal line connected to the fuse element of a fuse program circuit is coupled to a pad other than an internal circuit power supply pad, and it is intended to detect externally a minute current of the fuse element for detecting a fuse cut-off failure.
When a laser beam is to be used for programming such fuse elements, a laser apparatus for the fuse programming is required, and a step of transporting wafers from an inspection apparatus to the laser apparatus is necessary, resulting in problems such as wafer contamination.
For performing the fuse programming through laser beam irradiation, the fuse programming must be performed in a bare chip state because the fuse element cannot be radiated with the laser beam when the semiconductor chip is in a molded state. Therefore, it is difficult to implement the laser programming for failure repairing and others after packaging.
Storage capacity of an on-chip memory on a system LSI such as an SOC (System On Chip) has been increasing, and the faulty cell repair is required from the viewpoint of product yield. Likewise, in the case where a plurality of chips are used for constructing a system, as in an SIP (System In Package) or the like, necessity for repairing after molding is increasing for improving final yield. For example, when an SIP is formed of an inexpensive chip and an expensive chip stacked each other, if a fault is found in the inexpensive chip after packaging, the whole package becomes faulty, and the expensive chip is also treated as a faulty chip. Since each SIP has an optimum burn-in voltage different from others, it has been demanded to eliminate a burn-in step after packaging. Therefore, it is desired to assemble each chip, using a KGN (Known Good Die; a chip of which quality is ensured in an unassembled state).
Since the LT fuse is physically cut by the externally applied laser beam, the apparatus dedicated to trimming and the repairing step are required as already described, and the increase in cost due to investment on the apparatus as well as increase in TAT (Turn-Around Time) are unavoidable.
Instead of the above fuse programming through the laser trimming, electric fuses using, e.g., polycrystalline silicon (polysilicon) that is a gate electrode material are practically available. However, it is likewise necessary to arrange fuse elements with a small occupation area as the development of a miniaturizing process. The polysilicon that is the gate electrode material is the interconnects at the lowest interconnection layer, and peripheral circuits for supplying a current to the fuse elements and for determining an output level cannot be arranged near the fuse elements at high densities without difficulty. Therefore, it is difficult to reduce the occupation area of the fuse circuit including the fuse elements.
In Reference 1, the laser beam is used for blowing the fuse element. For overcoming a problem that the programmed state of the fuse elements cannot be changed after the blowing of the fuse elements, the scan shift circuit is used to set the state of the internal circuit according to the program information for testing the circuit operation before programming of the fuse elements. It is intended to facilitate the analysis for determining whether any fault is due to faulty fuse programming. However, Reference 1 discloses, as the fuse elements, only the LT fuse elements that can be blown through application of the laser beam, and Reference 1 does not consider fuse elements that can be electrically blown off.
Reference 2 discloses the arrangement of the interconnects or the elements in the layer under the fuse elements. However, the laser wavelength decreases with miniaturization of the fuse elements, and accordingly the laser energy increases. According to Reference 2, the impact interruption layer having a high melting point is arranged below the fuse element for reducing an impact to the lower layer portion that may be caused by the increase in laser energy as described above. It is intended to avoid the destruction of the elements in the lower layer. However, Reference 2 likewise gives no consideration to the structure or configuration for electrically blowing the fuse elements.
According to Reference 3, the pad connected to the fuse element and the pad connected to the internal circuit are made common, and a selection circuit selects the connection path of the pad according to a control signal. The fuse element is selectively blown by a current. In the construction disclosed in Reference 3, the current is selectively supplied to the fuse element to blow it according to the signal applied from the pad. Although some pads are shared, there are pads that are not shared, and the number of empty pads that are not used when the semiconductor device practically used, is increased. Although Reference 3 discloses the blowing of the fuse elements with the current, it does not disclose any specific layout of the fuse elements, power consumption and others.
In Reference 4, the power supply for supplying the current to the fuse element is commonly used for the power supply of the internal circuit. It is also disclosed that the fuse element may be of a current-blow type. In Reference 4, however, no consideration is given to the current consumption required for blowing the fuse element by the current. Also, the arrangement and interconnections of the fuse elements are not specifically disclosed.
A construction is also proposed in which a flash memory of an inverted gate structure is used for electrically programming fixed information. However, the flash memory is used, and a circuit construction for the programming is large, resulting in a problem that a fixed information program circuit of a small occupation area cannot be achieved without difficulty.